The present invention relates generally to the field of analog-to-digital converters and, more particularly, to a charge redistribution analog-to-digital converter that provides for asynchronously sampling signals in a fully powered-down state of the converter.
Analog-to-digital converters (ADCs) are well-known and are in widespread use. With the recent high growth of portable electronics systems, the requirement for long lasting low power battery operated systems has become paramount. ADCs are often required to take samples of randomly occurring events and thus must be able to idle for extended periods of time until these events occur. During that time, power is dissipated as the ADC system awaits in readiness to acquire these events. Generally, this xe2x80x9cstand-byxe2x80x9d power is associated with a reference or bias voltage either internal or external to the ADC. In order to extend battery life, many systems will essentially completely power down and awake when the random event occurs in order to be able to sample the event. This awakening process takes time and, thus, the actual capability to capture the event""s beginnings is curtailed.
There exists a need for an essentially completely powered down ADC system which can respond instantly to a sampling request.
One type of ADC is a so-called xe2x80x9cswitched-capacitor,xe2x80x9d or charge redistribution, converter in which an input voltage is sampled as charge across an array of capacitors during a first time phase. Thereafter, charge is redistributed as the converter determines a digital xe2x80x9cequivalentxe2x80x9d to the sampled input voltage. One well-known ADC that makes use of switched capacitor circuitry is the so-called successive approximation routine (SAR) converter.
A differential input, charge redistribution SAR ADC is shown in FIG. 1. It samples a pair of input voltages, Vinp and Vinn, with respect to a datum, or common-mode bias voltage, Vcm, and, under the control of a successive approximation routine (SAR) engine, produces a sequence of binary decisions at the output, OUT, which correspond to the digital equivalent of the input voltage difference with respect to the reference voltage difference, (Vrefpxe2x88x92Vrefn).
The ADC system 100 shown comprises two digital-to-analog converters (DACs), DAC-P and DAC-N, a comparator 12, and an SAR engine (not shown) to drive the DACs. Each DAC comprises (for this example) a 6-bit binary-weighted capacitor array 14P, 14N, where the total capacitance of each array 14P, 14N is C. The DACs further comprise two corresponding sets 16P, 16N of switches to connect the respective DAC inputs to Vinp/n, and corresponding sets 18P, 18N of switches to connect the respective DAC inputs to Vrefp/n, as well as switches 20P, 20N to connect the DAC outputs, TOP-P, TOP-N, to the datum or common-mode voltage point(s), Vcm.
In the example shown in FIG. 1, each of the weighted capacitor arrays 14N (associated with DAC-N) and 14P (associated with DAC-P) includes capacitors C1, C2, C3, C4, C5, C6 and C7. The capacitances of such capacitors, with respect to the total capacitance C of the array, is as follows: C1=C/2, C2=C/4, C3=C/8, C4=C/16, C5=C/32, C6=C/64 and C7=C/64. The sum of the capacitances of C1-C7 equals C.
Each of switch sets 16N (associated with DAC-N) and 16P (associated with DAC-P) includes switches S1, S2, S3, S4, S5 and S6. Each of switch sets 18N (associated with DAC-N) and 18P (associated with DAC-P) includes switches S21, S22, S23, S24, S25 and S26.
The DAC outputs TOP-P, TOP-N, provide input voltages to the comparator 12. The plates of the capacitors directly connected to the outputs TOP-P, TOP-N are referred to as the xe2x80x9ctop platesxe2x80x9d with the other capacitor plates referred to as the xe2x80x9cbottom plates.xe2x80x9d The switches to Vcm are referred to as the xe2x80x9ctop-plate switchesxe2x80x9d 20P, 20N.
During operation, an input voltage is sampled as charge across the input capacitors. With the DAC bottom plates connected to the input voltage Vinp and Vinn through switches 16P and 16N, when the top-plate switches 20P and 20N are closed, the DAC is said to be xe2x80x9csampling the inputxe2x80x9d, and the instant at which the top plate switches open, the DAC is said to have xe2x80x9ctaken the samplexe2x80x9d.
After sampling the input voltage, the SAR ADC 100 carries out an iterative process, referred to as a successive approximation routine (SAR). Using the P-side of the circuit as an example, the SAR iterative process begins by connecting the bottom plate of each of the capacitor array 14P capacitors C1 . . . C6, through its corresponding switch S1 . . . S6 in switch bank 16P and a corresponding switch S21 . . . S26 in switch bank 18P, to either the positive reference voltage Vrefp or the negative reference voltage Vrefn. Each capacitor, e.g. C4, represents one of the bits in the digital output word of the ADC 100, the most significant (MSB) of which corresponds to capacitor C1 and the least significant bit (LSB) of which corresponds to capacitor C6.
In an exemplary embodiment, a bit has a binary value of 1 when the bottom plate of the associated capacitor, e.g. C4, is connected to the positive reference voltage Vrefp and the bit has a binary value of 0 when the bottom plate of the capacitor, e.g. C4, is connected to the negative reference voltage Vrefn through switch bank 18. In this example, switch S4 would get switched to connect capacitor C4 to the Vref set (not the Vinp position) and switch S24 would get aligned to connect capacitor C4 to either Vrefp or Vrefn, depending on whether C4 was to represent a logical 1 or 0, respectively.
As those skilled in the art will appreciate, through such a series of SAR iterations, starting with the MSB capacitor and ending with the LSB capacitor, wherein, during each iteration, each capacitor is switched to either Vrefp or Vrefn such that the top plate voltages, TOP-P and TOP-N, converge with each iteration. When the iterations have completed, the last-used digital word (the value of the bits to which the capacitors were connected) is selected as the output of the ADC. These iterations are graphically depicted later.
For pseudo-differential operation, Vinn (often referred to as a xe2x80x9cground sensexe2x80x9d) is held at a voltage near Vrefn. The ADC 100 is powered by voltage supplies of VDD (positive) and VSS (negative) and the reference voltage inputs are Vrefp and Vrefn. The DAC top plates are sampled to Vcm, which is an arbitrary but constant voltage typically mid-way between VDD and VSS. Note that during sampling, TOP-P and TOP-N will be nominally held at approximately Vcm by the top plate switches.
FIGS. 2A-C show an aspect of the pseudo-differential operation of the DAC 100 of FIG. 1. FIGS. 2A-C, and all subsequent similar figures, depict the top plate voltages TOP-P, TOP-N after the sample is taken and the digital words shown are presented to the SAR-P and SAR-N switches. SAR-N=000000 in FIGS. 2A-C, and SAR-P values are shown along the horizontal axis for each of a number of iterations in the SAR process.
As an example, FIG. 2A shows the output voltage 202A of TOP-P, as well as voltage 204A for TOP-N with Vinp=Vrefn. The voltage 202A decreases monotonically, and the bit sequence at SAR-P is shown along the horizontal axis, and is 100000 at the first iteration and 010000, 001000, 000100, 000010, 000001 at subsequent successive iterations of the SAR.
FIG. 2B shows an analogous situation for voltages 202B below Vcm with Vinp=Vrefp. The TOP-P voltage 202B is monotonically increasing. The SAR-P bit sequence changes from initial value 100000 to 110000, 111000, 111100, 111110, 111111 on subsequent successive iterations of the SAR.
FIG. 2C shows the situation for Vinp=xe2x85x9c*Vrefp. The TOP-P voltage 202C here is not monotonic, and the SAR-P sequence is 100000, 010000, 011000, 010100, 010110, 010111.
The reader should note that, during the course of the SAR, several things occur. Firstly, the TOP-P node may undergo voltage excursions above and below the datum or common mode voltage, Vcm, as shown in FIGS. 2A-C. Secondly, the TOP-P voltage is driven by the SAR to progressively more closely approach the TOP-N voltage. This is indicated in FIGS. 2A-C, where in all three instances, voltages 202 and 204 converge after a number of steps. Thirdly, as the SAR progresses, there is a xe2x80x9ccritical decisionxe2x80x9d which may occur at any cycle (depending on the input being converted) characterized by TOP-P voltage 202 being essentially equal to TOP-N voltage 204. At this point the digital value of SAR-P represents the input voltage being converted. Fourthly, at the critical decision, the state of each of TOP-P and TOP-N is essentially the same as that when the sample was taken, i.e., both are at Vcm. The latter represents a xe2x80x9creturn-to-zeroxe2x80x9d condition whereby any system xe2x80x9cparasiticsxe2x80x9d, either linear or non-linear, and which would otherwise corrupt the conversion process, are essentially in the same state as they were during sampling and, thus, are prevented from contributing errors. It is for that reason that one strives to maintain the same value of Vcm for both sampling and conversion. Unfortunately, maintaining Vcm during sampling while awaiting a random instantaneous request to take a sample consumes some power in the ADC system.
FIGS. 3A-C show an attempt to eliminate Vcm to save power for a pseudo-differential system. For simplicity, the system of FIGS. 3A-C have the following alterations with respect to FIGS. 1 and 2A-C: Vrefp=VDD, Vrefn=VSS=Vcm=GND. It is the condition of Vcm=GND (zero power required) which is being highlighted in FIGS. 3A-C. Under these conditions, TOP-P is driven to voltages below ground up to an amount of half of the power supply, VDD. In general, whenever a circuit node exceeds the power supply voltages by more than a few hundred millivolts, a parasitic diode (not shown) turns on and current flows through that diode, often with detrimental consequences. In this case, the top plate switch parasitic diode turns on and the sampled charge on the capacitor array representing the sampled input voltage starts to flow through the diode and is lost. The subsequent conversion is corrupt and the digital answer will therefore be wrong.
FIGS. 3A-C depict the top plate voltages TOP-P, TOP-N after the sample is taken and ignoring the effects of any parasitic diodes. The digital words shown are presented to the SAR-P switches during the SAR algorithm. SAR-N=000000 in FIGS. 3A-C, and SAR-P values are shown for each of a number of iterations in the SAR process.
As an example, FIG. 3A shows the output voltage 206A of TOP-P, as well as voltage 208A for TOP-N with Vinp=GND. The voltage 206A decreases monotonically, and the bit sequence of SAR-P is shown along the horizontal axis, and is 100000 at the first iteration and 010000, 001000, 000100, 000010, 000001 at subsequent successive iterations of the SAR.
FIG. 3B shows an analogous situation for voltages 206B less than ground voltage when Vinp=VDD. The TOP-P voltage 206B is monotonically increasing. The SAR-P bit sequence changes from initial value 100000 to subsequent successive values 110000, 111000, 111100, 111110, 111111 on successive iterations of the SAR.
FIG. 3C shows the situation for Vinp=xe2x85x9c*Vrefp. The TOP-P voltage 202C here is not monotonic, and the SAR-P sequence is 100000, 010000, 011000, 010100, 010110, 010111.
It can be thus seen that attempting to eliminate all power sustaining Vcm by setting Vcm equal to GND will result in the turning on of any parasitic diodes present at the top plate.
One aspect of the invention is to boost the inputs to the comparator after sampling the input voltage but prior to beginning the successive approximation routine (SAR). The boost should avoid the problem of turning on diodes and enabling sampled charge to escape. As the routine iteratively progresses and the voltage differences between TOP-P and TOP-N become less and less, to a point where the voltage on an output node of a digital-to-analog converter (DAC) no longer would be able to turn on a diode, then the boost to the comparator inputs is removed.
More specifically, the invention will show how it is possible to make the above configuration with Vcm=GND during acquisition, and thus having essentially zero power dissipation during acquisition, and yet still yield accurate conversions.
The invention applies to numerous different types of ADCs, not just switched-capacitor ADCs. Also, it applies to any of differential, single-ended, pseudo-differential and quasi-differential ADCs.
One embodiment of the invention is directed to an analog-to-digital converter (ADC) including a switched-capacitor circuit that samples an input voltage onto a plurality of capacitors of at least one DAC. Assuming two DACs (which is the case in the differential version of the ADC of the invention), a comparator, coupled to the switched-capacitor circuit, compares the voltage across the DACs and directs an SAR algorithm to modify the DAC inputs such that the two DAC outputs converge. The common mode output voltage of the DACs is boosted during only some of the iterations.
According to another embodiment of the invention, a method of analog-to-digital conversion includes acts of: using a comparator to compare one input with another input during each of a number of iterations; and applying a common-mode boost to the comparator during at least some of the iterations.